Variable speed plural motor control system with incremental speed synchronization

ABSTRACT

A system for controlling the speed and synchronization of two ac motors comprises a master vco (voltage-controlled oscillator) for providing timing pulses to drive the master inverter which energizes the first a-c motor. A system speed control pot provides a speed set signal to the master vco, and also to a slave vco which controls the slave inverter that energizes the second a-c motor. A phase detector receives first and second lowfrequency input signals from the loads driven by the motors. A count-up register receives high-frequency pulse signals from the master vco and, through a dac (digital-to-analog converter), provides a positive-going ramp signal which has its reset portion determined by an output signal from the phase detector. A countdown register receives high-frequency pulse signals from the slave vco and, through another dac, provides a negative-going ramp signal which has its reset portion determined by a second reset signal from the phase detector. These opposite-slope ramp signals are summed with a signal from the phase detector to provide a d-c control signal which is used as a second input signal to the slave vco, thus maintaining motor synchronization. An out-of-sync signal overrides the d-c control signal and provides a modified d-c signal to the slave vco to drive the second motor toward synchronization. The d-c control signal can also be modified by a position control signal, to provide an incremental position variation of the second a-c motor without disturbing the synchronized speed relationship of the two motors.

United States Patent 1 Bejach VARIABLE SPEED PLURAL MOTOR CONTROL SYSTEMWITH FNCREMENTAL SPEED SYNCHRONIZATION [75] inventor: Benton Bejach,Santa Ana, Calif.

[73] Assignee: Borg-Warner Corporation, Chicago,

Ill.

22 Filed: April 13, 1971 21 Appl.No.: 133,650

Primary Examiner- T. E. Lynch Attorney-Donald W. Banner, William S.McCurry and James J. Jennings, Jr.

[57] ABSTRACT A system for controlling the speed and synchronization oftwo a-c motors comprises a master vco (volt- Speed f25 |nverter 24 MolorFeb. 27, 1973 age-controlled oscillator) for providing timing pulses todrive the master inverter which energizes the first ac motor. A systemspeed control pot provides a speed set signal to the master vco, andalso to a slave vco which controls the slave inverter that energizes thesecond a-c motor. A phase detector receives first and secondlow-frequency input signals from the loads driven by the motors. Acount-up register receives high-frequency pulse signals from the mastervco and, through a dac (digital-to-analog converter), provides apositive-going ramp signal which has its reset portion determined by anoutput signal from the phase detector. A count-down register receiveshigh-frequency pulse signals from the slave vco and, through anotherdac, provides a negative-going ramp signal which has its reset portiondetermined by a second reset signal from the phase detector. Theseopposite-slope ramp signals are summed with a signal from thephasedetector to provide a d-c control signal which is used as a second inputsignal to the slave vco, thus maintaining motor synchronization. Anout-of-sync signal overrides the d-c control signal and provides amodified dc signal to the slave vco to drive the second motor, towardsynchronization. The d-c control signal can also be modified by aposition control signal, to provide an incremental position variation ofthe second ac motor without disturbing the synchronized speedrelationship of the two motors.

13 Claims, 14 Drawing Figures Slave Position Phoselock 8 Poslhon COnlrolSystem Slove I 45 vco 4 inverler Inverter .PAIEN'IEUFEBZYISYS sum 1 or 548 S I I I I love Position 47 1 32 3 55 46 r f I 33 37 -I I 5| 54 38Phclselock 54 aposl-fion 43 Inverter Inverter Control System I I r ISlave 45 V00 Inventor Benton Be ach y I L r.

A torney PATENTEDFEBZ'IIHYS SHEET 5 OF 5 Attorne lnventor v BenronBGJOCh By m VARIABLE S IEED PLURAL MOTOR CONTROL SYSTEM WITH INCREMENTALSPEED SYNCIIRONIZATION BACKGROUND OF THE INVENTION In the motor controlart different systems have been developed and then improved in an effortto achieve not only good speed regulation but also synchronizationbetween the operating speeds of two or more electrical motors. Much ofthis effort has been expended on systems .which use a-c motors, becausethey are generally simpler, more rugged and less expensive than d-cmotors. One control system for synchronizing two motors utilizestachometers or other devices to provide signals indicating the actualrotation speeds of the motors, or the speeds of the loads driven by themotor. A phase detector circuit is frequently employed to compare thetwo speed-indicating signals, and thus indicate any speed (orsynchronization) difference by a change in the output signal of thephase detector. Such a system is helpful to achieve the same operatingspeeds or to maintain synchronization by maintaining the desired ratioof operating speeds between two motors but has not achieved the highdegree of precision necessary in many precise manufacturing-operations.

It is therefore a primary object of this invention to provide such aspeed control system which not only can maintain two motors operating atthe same speed or at synchronized speeds, but can also insure preciseinphase operation to maintain an exact physical correlation between thedriven loads.

I Another important object of this invention is to provide such a systemwhich can also produce a slight phase displacement in one motor controlsignal to produce a corresponding slight physical displacement of one ofthe motors, to adjust or change the relative positions of the drivenloads without losing the synchronized speed operation between the twoa-c mo,- tors.

SUMMARYOF THE INVENTION A variable speed motor control system drives afirst a-c motor from a first inverterwhich"receives timing pulses from amaster source, such as a vco (voltagecontrolled oscillator). A systemspeed control unit, such as. a potentiometer, is connected to regulatethe rate at which the timing pulses issue from the master source. Asecond a-'c motor is energized from a second inverter which receivestiming pulses from a slave source. I

Particularly in accordance with this invention, a phase-lock andposition control subsystem is provided.

This subsystem includes means for applying a signal.

from the system speed control unit to the slave source of timing pulses.A phase detector is included, and is connected to receive both a firstseries of position-indicating signals which varies as a function ofmovement of the firsta-c motor, and a second series ofposition-indicating signals which varies as a function of movement ofthe second a-c motor. A first register-and-dac is connected to receivean input signal from the master source, and to provide a first rampsignal having a slope of given polarity. The reset portionv of thisfirst ramp signal is determined. by a first reset signal from the phasedetector. A second register-and-dac is connected to receive an inputsignal from the slave source, and to provide a second ramp signal whichhas a slope with a polarity opposite that of the first ramp signal. Thesecond ramp signal is displaced in phase relative to the first rampsignal, and the reset portion of the second ramp signal is determined bya second reset signal from the phase detector. A summing means isprovided for combining the ramp signals with the phase detector signalto provide a d-c control signal at a summation point, and this d-ccontrol signal is applied to the slave source of timing pulses. Withthis system synchronized operation between the first and second a-cmotor is achieved and maintained.

In accordance with another aspect of this invention, the subsystem mayinclude a position control unit for the second (or slave) a-c motor. Theposition control unit can be a potentiometer coupled to the summingmeans for combining the ramp signals. Adjustment of the position controlpotmodifies the d-c control signal and produces an incremental positiondisplacement of I the second a-c motor with respect to the first. Thisis accomplished without disturbing the syn-chronized operation betweenthe two motors.

THE DRAWINGS FIGS. 4 and 5 are schematic diagrams illustrating circultdetails of the system shown more generally in FIG. 2.

GENERAL SYSTEM DESCRIPTION FIG. 1 depicts a general material transportarrangement in which a reference conveyor belt 20 is driven over amechanical coupling 21 from a first a-c motor 22. In turn the a-c motoris energized over line 23 by the a-c voltage output from a firstinverter 24. The frequency of inverter operation is determined by timingpulses'received over line 25 from a master source of timing pulses,depicted'with the general legend of a voltage controlled oscillator(vco). The rate at which these timing pulses issue from vco 26 isdetermined by a speed set signal received over line 27 from a systemspeed control unit 28. This unit can be a potentiometer, as shown, orany other suitable means of providing an adjustable d-c voltage toeffect a variation in the frequency of the pulses provided by master vco26. Thus the setting of speed pot 28 regulates the rotational speed ofmotor 22, and thus governs the rate of linear displacement of conveyorbelt 20.

For purposes of explaining the invention it is as sumed that subassemblyconveyor belts 30 and 31 are arranged at right angles to the main belt20, to feed material or parts toward (and perhaps onto) main belt 20 ata rate which should be precisely synchronized with the speed of the mainbelt 20. Precise synchronization, as used in this specification and theappended claims, does not mean only an exact l:l correspondence betweenthe speeds of the conveyor belts or their driving motors. It may be thatthe subassembly conveyor 30 carries units to be assembled in a mannersuch that four units from belt 20 are to be attached directly to asingle component passing on main conveyor 20. In

this case the auxiliary belt 30 would be driven four.

times as fast as main conveyor belt 20. Thus the term synchronizationembraces both 1:1 correspondence, and other ratios of speeds between theconveyor belts and their driving motors.

The subassembly belt 30 is driven over a mechanical linkage 32 from asecond a-c motor 33, which in turn is energized over line 34 from asecond or slave inverter 35. The additional subassembly conveyor 31 issimilarly driven over a linkage or shaft 36 from a third a-c motor 37,which is energized over line 38 from a third inverter 40. The subsequentexplanation will make it evident that additional motors and theirenergizing inverters can be utilized, and driven in synchronization withthe master motor 22 which drives the main conveyor 20. The principles ofthis invention will be described in connection with the drivingrelationship between the master motor 22 and the slave or second motor33.

Slave inverter 35 has the frequency of its output voltage determined bypulses received over line 41 from a first output connection of a slavevco 42. Particularly in accordance with this invention, a phaselock andposition control subsystem 43 is provided. The subsystem 43 receivesfour different input signals and provides a single output control signalover line 44 to regulate the frequency of the slave vco, in conjunctionwith another signal received over line 45 from the speed pot 28 whichalso determines the frequency of the pulses from master vco 26.Subsystem 43 receives a first series of position-indicating signals overline 46 from a first detector 47 positioned adjacent main conveyor belt20. The sensor 47 can be a magnetic type unit which issues an outputpulse over line 46 each time one of the magnetic units 48, embedded inthe conveyor belt, passes detector 47. These magneticunits 48 are spacedapart by a distance indicating a single work space, or other arbitraryinterval, in accordance with the individual manufacturingspecifications. A similar series of magnetic reference markers 49 areembedded along the edge of slave conveyor belt 30, so that passage ofeach marker 49 adjacent detector 50 provides one of a second series ofposition-indicating signals for application over conductor 51 to thesubsystem 43. It is emphasized that although the detectors 47, 50 areshown positioned adjacent the loads driven by the respective motors 22and 33, the detectors could also be positioned to sense rotation of theoutput shafts of the a'c motors before this rotational movement istranslated into linear displacement. Likewise other types of sensorscould be employed. Photocells can be utilized and energized as lightpasses from a lamp through spaced-apart timing holes near the edge ofthe conveyor belts to strike the photocells and provide the first andsecond series of position-indicating signals to denote in some way theoperating speeds of the motors 22 and 33, which in this example isaccomplished by sensing movement of the loads driven by these motors.

Subsystem 43 receives a third input signal over line 52 from master vco26, a signal similar to that of the train of pulses applied to themaster inverter. A fourth input signal to the subsystem is received overline 53 from slave vco 42, and this fourth signal is similar to thetrain of timing pulses which regulates the frequency of slave inverter35. It is noted that these third and fourth subsystem inputs are at ahigh frequency, that is, high with respect to the low-frequency inputsignals received over lines 46 and 51. To illustrate it is assumed thatmaster vco 26 is providing pulses on lines 25 and 52 at 360 Hertz. Witha three phase inverter,

utilizing two semiconductor switches in each phase, this train of pulseswould be divided by six in a well known circuit (not illustrated), sothat the output voltage of inverter 24 would be alternating at 60 Hertz.A four-pole motor 22 would thus be driven at 1,800 rpm, or 30revolutions per second (rps). Another frequency reduction is generallyprovided in gearing (not shown) between the motor shaft 21 and thedriven load 20. If this reduction of the order 20:1, then the-outputshaft speed is 1.5 rps. Thus the actual linear displacement of belt 20is such that the signals from sensor 47 occur at 1.5 Hertz. Thefrequency of the signals on lines 46 and 51 is low when contrasted tothe frequency of the vco signals on lines 52 and 53. The fifth inputsignal to subsystem 43 is provide over line 54 from a position controlunit, depicted as a potentiometer 55. As will become apparent from thesubsequent explanation, a change in the voltage level passed over line54 provides a slight position change at the output shaft of slave motor33, with a consequent adjustment of the linear position of auxiliaryconveyor belt 30 relative to belt 20. his important to note that thisposition control to provide precise alignment of the 1 work stations iseffected without disturbing the continued synchronization between theoperation of master motor 22 and slave motor 33.

DETAILED DESCRIPTION OF THE INVENTION FIG. 2 depicts the majorcomponents of subsystem 43, their connections with the master'andslavevcos, and with the low-frequency signal detectors 47, 50'. Thesubsystem 43 includes a phase detector 60, having two inputconnectionsfor receiving the low-frequency position-indicating signalsover conductors 46 and 51. It is assumed for purposes. of 1 thisexplanation that the system of FIG. 1 is driving the motors 22 and 33,and thus belts 20 and 30, at the same speed, and that the subsystem ismaintaining a precise 1:1 synchronization between the motor speeds.Under these conditions magnetic markers 48 pass detector 47, and a firstseries of low-frequency position-indicating signals 61, as shown in FIG.3A, is passed over line 46 to phase detector 60. These signals 61 varyas a function of movement of first motor 22, and of primary conveyorbelt 20. Under in-sync conditions, detector 60 is also receiving asecond series of low-frequency position-in-dicating signals 62 (FIG-3B)over line 51 from detector 50. The physical position of either or bothdetectors 47 and 50 can be adjusted to provide the spacing of pulses 61and 62 shown in FIGS. 3A and 33 when the system is in synchronization.If the auxiliary or slave conveyor 30 is driven faster than belt 20, acount-down unit (not shown) can be coupled in series with line 51 tocompensate for the speed difference. For example, if belt 30 were driventwice as fast as belt 20, then such unit would pass a single outputpulse over line 51 for each two pulses received from detector 50. Theposition-indicating signals 61, 62 govern phasedetector 60 in thegeneration of a square-wave signal 63 as shown in FIG. 3C. Thepositive-going portion of each pulse, referenced 64, is determined asmagnetic marker 48 passes detector 47 and signal pulse 61 is appliedover line 46 to the phase detector. The term determined means theoccurrence in time, as used in this explanation and in the appendedclaims. Similarly the negativegoing portions65 of the waveform 63 aredetermined upon each receipt of a signal over line 51 from detector 50adjacent slave conveyor belt 30.

As each reference pulse 61 is received over line 46, conventionalcircuitry within the phase detector reshapes the pulse. The reshapedpulse is passed as a reset or trigger signal over line 66 to a firstinput connection of a first register 67. This first register or counteris termed a count-up register because, after being reset by alow-frequency sig-nal such as 61 received over line 66, the registerbegins to count or total the high-frequency pulses received over line 68from the master vco '26. A divide-by-two circuit 70 is shown coupledbetween master vco 26 and the countup register 67. The divide-by-twocircuit 70 can be bypassed by closing switch 71. Those skilled in theart will understand the divide-by-two circuits permit the use of largerspeed reduction ratios, since ratios larger than that given in theexample about (36011.5) require more count-up register capacity.

After reset, register 67 begins to accumulate the high-frequency timingpulses received over line 68. A digital-to-analog converter (dac) 72 isshown coupled over first and last lines 73, 74 to count-up register 67.Line 73 is shown at the least significant bit (lsb) end of the dac. Line74 is adjacent the most significant bit (msb) end, and is actuallycoupled to the msb-l connection. Of course there are at least eightadditional connections between lines 73 and 74, but they are omitted forthe sake of describing the system concept and signal flow. The actualmsb connection of dac 72 is coupled over variable resistance 99, andconductors 108, 109 to phase detector 60. With this arrangementadjustment of resistor 99- regulates the weighting of the phase detectorsignal to match the exact high/low frequency ratio of each particularequipment installation. This high/low frequency ratio can be any real,non-integer number. Moreover the master and slave high/low frequencyratios need not be identical. The digital total accumulated in count-upregister 67 is translated into an analog signal in dac 72, and thisanalog signal is passed over conductor 75, first summing amplifier 76,first mixing resistor 77 and conductor 78 to summation point 80. Ofcourse the same potential or'same signal which appears on conductor 78is also present at point 80, but it is convenient to have a singlereference such as summation point" to characterize the location at whicha d-c control signal will be developed to assist in regulating slave vco42.

Another way of viewing the first register-and-dac combination 67,72 isto consider them as a single function generator. Such a generatorproduces a waveform of the type referenced 81 in'FIG. 3D. This firstramp signal 81 has its reset portion 82 in each cycle determined byreceipt of a first reset signal over line 66 from the phase detector.The slope of first ramp signal 81 is represented by portion 83, and theamount of slope is a function of the rate at which the high-frequencytiming pulses are received over line 68.

Another register-and-dac combination is provided, including a count-downregister 84 and its dac 85. Lines 86 and 87 provide the lsb and msbconnections between the register and the dac; the additional connectionsare omitted for the sake of simplifying the discussion. High-frequencytiming pulses from slave vco 42 pass over line 53, divide-by-two circuit88, and line 90 to the count-down register. A switch 91 is provided tobypass circuit 88 when required to accommodate a larger than normalspeed (frequency) ratio. Register 84 also receives a reset signal overline 92 from phase detector 60. The reset signal is similar to thelow-frequency position-indicating signal 62 shown in FIG. 38. Each pulse62 is reshaped in phase detector 60, and then passed over line 92 to thecount-down register 84. The total of the high-frequency pulses receivedover line 90 is continuously accumulated in register 84 and converted indac 85, to produce a second ramp signal shown as 93 in FIG. 3B. Resetportion 94 of this second ramp signal 93 is virtually coin cidental intime with the slave marker pulse 62, and the sloping portion 95 of thissecond ramp signal has its degree of slope vary with variation of therate at which high-frequency timing pulses are received from slave vco42. Thus the second ramp signal 93, displaced in phase with respect tothe first ramp signal 81 as shown, is passed over conductor 96, a secondsumming amplifier 97 and second mixing resistor 98 to summation point80. The summing amplifiers 76, 97 and their respective mixing resistors77, 98 can be considered as a means for combining the ramp signals toprovide a d- 0 control signal at the summation point.

Inspection of the first and second ramp signals 81 and 93 shows that bycombining these signals a square wave signal 100 (FIG. 3F) will beproduced. The sloping portions of the ramp signals have oppositepolarities and thus produce a virtually constant d-c voltage. I-Iow everthe first negative-going transition 82 of the first ramp 81 is reflectedas the negative-going portion 101 of the square wave 100, and thepositive-going orreset portion 94 of the second ramp signal 93 appearsas the portion 102 of the resultant square wave. Inspection also showsthis resultant square wave 100 is a mirror image of the square wavesignal 63 produced by phase detector 60. Accordingly signal 63 is passedover lines 109, 108 and resistor 99 to the msb connection of dac 72,where it is added to the first ramp signal 81. The effect of thisaddition is to displace the first ramp signal 81 by l, and thus theresultant signal which appears at summation point 80 will be a virtuallyconstant d-c control signal.

This d-c control signal is passed from summation point 80 through anamplifier-and-filter stage 100, which includes a local bias adjustingunit 101for regulating the gain of an amplifier stage within circuit100. The d-c control signal is then passed from circuit over theeffective portion of a variable resistor 102 to line 44. Adjustment ofthe system gain unit 102 regulates the loop gain in the feed-back systemover line 44 to slave vco 42. The d-c control signal on line 45 is mixedwith the d-c control signal received over line 44 within slave vco byany conventional mixing circuit (not shown). This circuit can be a pairof equal-value resistors connected in the mixing arrangement in much thesame way-resistors 77, 98 are tied to a common summation point 80. Ineffect the first d-c signal from speed control pot 28 applied over line45 insures that slave vco 42 produces timing pulses which will maintainslave motor 33 in precise synchronization with the master motor 22. Thed-c control signal passed from summation point 80 over line 44 to theother input connection of slave vco 42 is exactly the same d-c level asthat received over line 45 when the system is operating insynchronization.

In accordance with an important aspect of this invention, the movablearm of position control unit 55 can be displaced to effect a slightposition change of auxiliary conveyor 30 relative to the referenceposition of master conveyor 20. Normally the movable arm of from normalsystem operation with synchronization between the motors. The value ofmixing resistor 103 is small, preferably at least an order of magnitudesmaller, than the values of the mixing resistors 77 and 98. Thus achange in the potential'at the. movable tap of position control pot 55in effect swamps out the normal d-c control signal provided over thesumming amplifiers. This produces a modified d-c signal at summationpoint 80, which signal is passed over the feedback loop and line 44 tothe slave vco. The result of this a-c voltage change is to produce aslight phase unbalance of the system which in turn results in acorresponding incremental physical change in the position of slave motor33 and thus of auxiliary conveyor belt 30. Following adjustment of slaveposition pot 55, the phase detector and dac signals will automaticallyreadjust such that the summed signal level at point 80 is identical tothe level which existed before the adjustment was made.

One way of viewing this controlled phase displacement to produce aposition change is to consider two cars moving in the samedirection andatpreciselythe same speed on -a highway. If both cars are travelling at60 mph, they are always maintained at precisely the same relativepositions. Suppose the driver of the trailing car desires tomaintain thesame speed, but also wants to pass the leading car. To do this heaccelerates for a brief time to move out and pass the lead car, and thenpulls back into the lane to become the lead car at exactly the samespeed as the car he just passed. Once again there is a steadyrelationship in the relative positions of the two cars. This analogy isnot perfect, but it conveys somewhat of the operation in which the slaveconveyor can be adjusted in position relative to the main conveyor, toobtain precise alignment of the complete system. l

The effect on the system of FIG. 2 of adjusting the tap of positioncontrol pot 55 is shown in FIG. 3G. The normal phase detector outputsignal 63 is there shown on a scale expanded relative to that of FIG.3C. By modifying the resultant d-c voltage at summation point 80, thetrailing or negative-going portion of the waveform can be displacedapproximately plus or minus 25 percent to produce a corresponding linearadjustment range of the auxiliary conveyor belt. The trailing edge 65can be moved" to the left, to the position referenced 104, or the pulsewidth can be extended and edge 65 moved to the right to the pointreferenced 105. The phase adjustment thus afforded represents animportant motor control system improvement which is achieved by thisinvention. However the enhanced operating accuracy, or maintainingprecise synchronization as achieved by the inventive system, is of greatimport even without any position control adjustment.

By way of example, the phaselock position control subsystem can beutilized to regulate induction motors. Position accuracy of such asystem is less than that achieved with synchronous motors, because withan induction motor the slip varies with the load and thus degrades theresultant accuracy. However for those systems with a relatively constantload, or those which are load cycled at the same rate as the job space(magnetic marker intervals), system accuracy can be provided within 1percent. The effects of variation in load in a system utilizinginduction motors are shown in FIGS. 3H, 31 and 3]. The normal in-synccondition with a resultant waveform 63 is repeated in FIG. 3H. With apercent load on the slave motor only, the phase detector output signalwould be modified approximately to that depicted as signal '106 in FIG.31. A 50 percent load would modify the phase detector-output signal toproduce that identified as 107 in FIG. 3.]; Even with these slightchanges the synchronization of the two induction motors is maintainedwith the system shown in FIG. 2. Slave vco 42 operates at a higherfrequency than does master vco 26, thus compensating for the slip rpminherent in the induction motor.

Another important component of the invention is the out of-sync circuit110 shown in FIG. 2. Circuit 110 receives a first signal from the phasedetector 60over line 111, in effect telling the out-of-sync circuit 110whether the system is in phase or out of phase at a given moment. Thisphase condition is readily determined by a simple circuit within phasedetector 60, which comparesrec'eipt of the reference markerpulses 61with receipt of the slave marker pulses62. As long asthese pulses arereceived alternately, it is manifest that the system is operating insync; this is indicated by a logic signal passed over line 111 tooutof-sync circuit 110. The sense of this logic signal is reversed iftwo reference marker pulses 61 are received without the interveningreceipt of a slave marker pulse 62, or if two marker pulses 62 arereceived without receiving any reference marker 61. The other logicsignal applied over lines 109 and 112 indicates whether the system isunder or over speed when an out-of-phase condition exists. This is alsosimply determined in the phase detector. If two reference pulses 61 arereceived before one slave pulse 62, then the system is under speed, anda first logic signal is provided over conductors 109, 1 12. However iftwo slave pulses 62 are received before a single reference marker 61,then the system is over speed, and the opposite sense of logic signal isprovided over conductors 109 and 112 to out-of-sync circuit 110. Thedetails and operational description of circuit 110 will be givenhereafter in connection with FIG. 5. For the present it is sufficient tonote that whenever the system is out-of-phase, an appropriate correctingsignal is passed from out-of-sync circuit 110 over line 113 and a fourthmixing resistor 114 to summation point 80. Like the third mixingresistor 103, the value of the fourth mixing resistor 114 is small withrespect to the values of the first two mixing resistors 77 and 98.Accordingly any correction signal provided by the out-ofsync circuitalso swamps the normal d-c control signal at summation point 80,providing a modified d-c signal which is passed over circuit 100, systemgain pot 102 and conductor 44 to the other input connection of slave vco42. This signal is in a direction to correct the operation of the systemby changing the frequency of the timing pulses issued from slave vco 42over line 53 to the count-down register 84.

PHASE DETECTOR CIRCUIT 60 Integrated circuits (ICs) are now available tosupply the functions of phase detector 60. One such IC is the MotorolaMC4044. The interconnection and operation of such phase detectors willbe understood by those skilled in this art.

' REGISTERS-AND-DACS: FIG. 4

FIG. 4 illustrates the provision and interconnection of a plurality ofintegrated circuits to form the count-up and count-down registers andtheir associated dacs. The modules designated U-l through U-8 can beFairchild 9093 modules, each of which comprises two flip-flops. Thoseskilled in the art will appreciate that other logic circuits can besubstituted, to provide a divide-by-four function in each of themodules. The pin 1 connections from 1 through 14 are shown in sequencearound each of the modules U-l through U-8. In addition, pins 1, 7, 8and 14 are identified to assist those skilled in this art tointerconnect and operate this invention. The two modules designated 135and 136 representcurrent sources, each individually coupled between itsassociated register and dacjThese units can be Fairchild 722 typesources or other suitable units. The pin connections are also indicatedin sequence, with numbers 1, 12, 13 and 24 being inserted to assistthose skilledin the art to make the interconnections most expeditiously.The dacs 72 and 85 can be resistive lattice networks, for example; ofthe MEPCO type MC400-l4. The l, 8, '9 and 16 pins are identified inthese networks to depict their intercoupling with the associated currentsource and register.

Line 137 receives a plus 6 volt potential, as does line 138, at thebottom of FIG. 4, applying this potential to the 7 pin of each ofthemodules in the registers. A voltage of plus 1 1- volts isapplied overconductor 140. With this arrangement the required count-up ramp signalis provided on line 75, and the-second or count-down ramp signal on line96,-as described previously in connection with FIG.2.

OUT-OF-SYNC CIRCUIT,SUMMING AMPLIFIERS, AND AMPLIFIER-AND-FILTERCIRCUIT: FIG. 5.

In FIG. the legends for the appropriate energizing voltage levels areshown-adjacentthe terminal connections in the different stages/This isespecially helpful in sistor 144 and the output connection of summingamplifier 97 to provide gain adjustment. The adjustment trimsthe gain ofamplifier 97, such that under normal conditions the sloping portions 83and 95 of waveforms 81 and 93 are identical in slope. This is requiredbecause even precision dacs are not matched to one another. These stagesprovide a d-c control signal at summation point 80 as previouslydescribed.

'Considering now the out -of-sync circuit 110, a pair of NPN typetransistors 147 and 148 are connected in the circuit, together with afield-effect transistor (FET) 150. Zener diodes 1'51 and 152 are alsocoupled in this circuit as shown.

For purposes of this explanation, it is assumed that a logical 1 signalis a positive signal, of a level sufficient to rapidly drive ontransistors 147 and 148. When this entire system is operating normallyand the desired synchronized relationship is maintained between themaster and slave motors, then the signals on lines 111, 112 are logicalzeros and circuit 110 does not operate to modify the d-c control signalat summation point 80.

Considering first the start-up condition of the system, this is similarto an underspeed condition, where underspeed signifies that the slavemotor is operating at a speed under that indicated by the setting ofspeed control pot 28. In this underspeed condition, two reference ormaster pulses arrive over line 46 at phase detector 60 without theintervening receipt of a slave marker pulse over line 51. This producesav logical 1, or positive, signal at the output side of phase detector60. This signal is passed over lines 109 and 112, Zener diode .151 andresistor 153 to the base of transistor 148,

' rapidly saturating this transistor. The emitter of transistor 148 iscoupled over a series circuit including resistors 154 and 155-to anenergizing terminal,.and its collector is coupled over another resistor156 to another energizing terminal. A plus 20 volts potential is appliedto both these terminals. With this rapidsaturation of transistor 148,the potential at its collector. goes negativeand this negative-goingsignal is applied over line 157 to the drain of FET 150.

Receipt of the two successive master marker pulses at phase detector 60without any receipt of a slave marker signal also causes a positive orlogical 1 signal to appear at the output terminal coupled to conductor111. This signal is applied over line 111 and resistor 158 to the baseof transistor 147, and rapidly saturates this transistor. The collectorof transistor 147 is coupled over resistor 160 men energizing terminalwhich receives a plus 25 volt potential, and the collector is alsocoupled over a resistor 161 to the gate of FET 150.

When transistor 147 wasstill non-conducting, a positive potential wasapplied over resistors 160 and 161 as a pinch-off voltage for FET 150.When the logical one signal is received over line 111 and transistor 147is saturated, the potential at its collector rapidly goes negative andthus the pinch-off voltage is removed from the gate of PET 150.Accordingly the negativegoing signal on line 157 which is appearing onthe drain of FET 150 now appears on its source. This negativegoingsignal is passed over line 113 and mixing resistor 114 to summationpoint 80. Like mixing resistor 103, the resistance value of mixingresistor 114 is small, preferably at least an order of magnitudesmaller, than the values of the first and second mixing resistors 77 and98. Accordingly the d-c control signal at summation point 80 which wouldotherwise be passed to the slave vco 42 to regulate its speed is swampedout by the negative-going signal received over mixing resistor 114 fromthe out-of-sync circuit. As will be explained hereinafter, anegative-going signal at point 80 is inverted in circuit 100, and apositive-going signal is applied to slave vco 42. The effect of thispositive change in the level of the modified d-c voltage applied overline 44 to slave vco 42 is to increase the frequency of the pulsesapplied over line 41 to slave inverter 35, to correct the underspeedcondition.

Operation to correct an overspeed condition, which also occurs when thesystem is being shut down, is related to that just described. In theoverspeed condition there is also an out-of-sync signal, or a logical 1,applied over line 111 to saturate transistor 147 and remove thepinch-off voltage from FET 150. In the overspeed mode, two slave markerpulses arrive at phase detector 60 without the intervening receipt of amaster pulse. This produces a logical zero or negative signal on lines109 and 112, and transistor 148 remains non-conducting. The positivesignal at the top of resistor 156 is thus applied over line 157 to thedrain of FET 150, and is passed to its source, over line 113 and mixingresistor 114 to summation point 80. Ultimately this positive-goingsignal is inverted to a negative change on line 43, and has the oppositeeffect of that just described. The result is a reduction in thefrequency of the vco pulses applied over line 41 to the slave inverter35. v

Within amplifier-and-filter circuit 100 a pair of op amps 162 and 163are illustrated. These can be Fairchild 741 units, like the summingamplifiers 76 and 97.'In the first amplifier stage the negative or 2 pinis connected to summation point 80, and 'also to one side of a parallelcircuit including a capacitor 164 and a resistor 165. The other side ofthis parallel circuit is coupled to the output side of amplifier 162.The other input connection of this amplifier is coupled over resistor166 tothe movable tap of a local bias adjust potentiometer 101, which iscoupled in a voltage divider circuit between resistors 167 and 168.

Between the output side of amplifier 162 and the 3 pin of amplifier 163is a filter circuit 170. The filter circuit includes aparallel-connected portion, having a resistor 171 and a capacitor 172,in the signal path.

Between this parallel-connected circuit and ground is a series circuitincluding a resistor 173 and a capacitor 174. Suitable values for thesecomponents and the other circuit components depicted in FIG. 5 will begiven below to simplify practice of the invention.

A feedback resistor 175 is coupled between the out put side of op amp163 and the 2 pin at its input side.

System gain control 102 is shown as a variable resistor coupled betweenop-amp 163 and the conductor 44 which passes the d-c regulating signalto one input connection of slave vco 42. The system gain can beregulated either by adjustment of system gain pot 102 or of the localbias adjust unit 101. I

To illustrate the operation, in the overspeed condition a positive-goingsignal is applied from FET to summation point 80, and thus to op amp162. This signal is inverted in stage 162 and a negative-going signalappears at its output, which is passed over filter to the 3 pin of opamp 163. There is no inversion in stage 163, and thus a negative-goingsignal is passed over line 44 to slave vco 42. This negative-goingsignal slows down vco 42, or reduces the frequency of the timing pulsespassed over line 41 to the slave inverter 35.

In out-of-sync circuit 110, Zener diode 151 was a 1N706A, and 152 was a1N747 type. The energizing voltages are shown on the schematic, and thevalues of the capacitors in microfarads and the resistors in ohms areset out below.

It is understood that these are typical operating values to enable oneskilled in this art to implement the invention with a minimum ofexperimentation. In nosense are these values, or the previousidentification of integrated circuits and othercomponents, a limitationon the basic concept and system configurations of this invention.

SUMMARY The present invention provides a high degree of accuracy in asystem for synchronizing the rotation of two or more a-c motors. It isagain emphasized that this system, with or without a position controlunit such as potentiometer 55, has utility with induction motors. Forgreater accuracy synchronous motors can be employed. In the systemswhich use synchronous motors, measuring accuracy (relative to thedriving motors or to the driven loads)has been as low as one-fourth of 1percent of one job space. With adjustment of position control unit 55, arange of adjustment of plus or minus 40 percent of a job space isreadily obtainable, to afford precise operation of the slave motor ordriven load relative to the master reference, whether a master conveyorbelt or the master motor. Overall system accuracy of 1 percent of a jobspace or work position interval has been achieved.

While only a particular embodiment of the invention has been describedand illustrated, it will be understood that various modifications andalternations may be made therein. It is therefore the intention in'theappended claims to cover all such modifications and alterations as mayfall within the true spirit and scope of the invention.

What is claimed is:

1. A variable speed motor control system for driving a first a-c motorenergized from a first inverter which receives timing pulses from amaster source, including a system speed control unit connected toregulate the rate at which the timing pulses issue from the mastersource, a second a-c motor energized from a second inverter whichreceives timing pulses from a slave source, and the improvement whichcomprises a phaselock and position control subsystem, including:

means for applying a signal from the system speed control unit to theslave source of timing pulses,

a phase detector, connected to receive a first series ofposition-indicating signals which varies as -a function of move-ment ofthe first a-c motor and to provide a first reset signal upon receipt ofeach position-indicating signal in the first series, and also connectedto receive a second series of position-indicating signals which variesas a function of movement of the second a-c motor and to provide asecond reset signal upon receipt of each positionindicating signal inthe second series,

first register-and-dac, connected to receive an input signal from themaster source and to provide a first ramp signal with a slope of givenpolarity, and also coupled to said phase detector so that the resetportion of the first ramp signal is determined by said first resetsignal,

a second register-and-dac, connected to receive an input signal from theslave source and 'to provide a second ramp signal with a slope having apolarity opposite that of the first ramp signal and displaced in phaserelative to the first ramp 'signaL-and also coupled to said phasedetector so that the reset portion of the second ramp signalis'determined by said second reset signal,

summing means for combining the ramp signals to provide a d-c controlsignal at a summation point, and

means for applying the d-'c control signal to the slave source of timingpulses, to maintain synchronized operation between the first and seconda-c motors.

2. A variable speed motor control system asclaimed in claim 1, in whichthe subsystem furthercomprisesa position control unit, coupledto thesumming means, such that adjustment of the position control unitmodifies the d-c control signal and produces an incremental positiondisplacement of the second a-c motor with respectto the first'a-cmoto'r, without disturbing the,

synchronized operationbetween thetwo motors.

3. A variablespeed' motor control system asclaimed in claim 1, in whichthe summing meanscomprises first and second summing amplifiersrespectively coupled to the dacs, and a pair of mixing resistors, eachcoupled between the summation point and one of the summing amplifiers,such that the d-c control signal is provided at the summation pointfo'rapplication to the slave source of timing pulses.

4. A variable speed motor control system' as claimed in claim 1, inwhich the subsystem further comprises an out-of-sync circuit connectedto receive both a first signal from the phase detector indicatingin-phase and out-of-phase operation, and asecon'd signal from the phasedetector indicating under-speed and over-speed conditions when thesystem is out-of-phase, and means coupled between the out-of-synccircuit and the summing means, to override the d-c control signal whenthe system is out of phase and pass to the slave source a modified d-csignal to drive the system toward in-phase operation.

5. A variable speed motor control system as claimed in claim 1, in whichthe subsystem further comprises an amplifier-and-filter circuit, coupledbetween the summing means and the slave source of timing pulses,including means for adjusting the gain of the system and thus ad-justingvariations in the duty cycle of the phase detector to maintain systemaccuracy.

6. A variable speed motor control system for driving a master a-c motorenergized from a master inverter which receives timing pulses from amaster vco, including a system speed control unit connected to regulatethe rate at which the timing pulses issue from the master vco, and aslave a-c motor energized from a slave inverter which receives timingpulses from a slave vco, characterized by a phaselock and positioncontrol subsystem which includes:

means for applying a signal from the system speed control unit to theslave vco,

a phase detector, connected to receive a first series of low frequencyposition indicating signals which varies as a function of movement ofthe master a-c motor and to provide a first reset signal upon receipt ofeach position indicating signal in the first series, also connected toreceive a second series of low frequency position indicating signalswhich varies as a function of movement of the slave a-c motor and toprovide a second reset signal upon receipt of each position indicatingsignal in the second series, and also connected to provide a square waveoutput signal in which the positive-going and negative-going portionsare determined by the first and second series of low frequency positionindicating signals,

a count-upregister-and-dac, connected to receive a high frequency inputsignal from the master vco and to provide a first ramp signal with apositive slope, and also coupled to the phase detector so that theresetportion of the first ramp signal is determined by receipt of saidfirst reset signal,

a count-down register-and-dac,connected toreceive ahi'gh frequency inputsignal from the slave vco andto provide a second ramp signal with anegative'slope, which secondrarnp signal is displaced in phase withrespect to the first rampsignal, and also coupledto the phase detectorso that the reset portion of the second ramp signal is determined byreceipt of said-secondreset signal,

summing means for combining the positive-slope and negative which thetiming pulses issue from the master vco, and a slave a-c'motor energizedfrom a slave inverter which receives timing pulses from a slave vco,characterized by a phaselock and position control subsystem whichincludes:

means for applying a signal from the system speed control unit to theslave vco,

a phase detector, connected to receive a first series of low frequencyposition indicating signals which variesasa function of movement of themaster a-c motor and to provide -a first reset signal upon receipt ofeach position indicating signal in the first series,also connected toreceive a second series of low frequency position indicating signalswhich varies as a function of movement of the slave arc motor and toprovide a second reset signal upon receipt of each position indicatingsignal in the second series, and also connected to provide a square waveoutput signal in which the positive-going and negative-going portionsare determined by the first and second series of low frequency positionindicating signals,

a count-up register-and-dac, connected to receive a high frequency inputsignal from the master vco and to provide a first ramp signal with apositive slope, and also coupled to the phase detector so that the resetportion of the first ramp sig-nal is determined by receipt of said firstreset signal,

a count-down register-and-dac, connected to receive a high frequencyinput signal from the slave vco and to provide a second ramp signal witha negative slope, which second ramp signal is displaced in phase withrespect to the first ramp signal, and also coupled to the phase detectorso that the reset portion of the second ramp signal is determined byreceipt of said second reset signal,

summing means for combining the positive-slope and negative-slope rampsignals with the phase detector square wave output signal to provide ad-c control signal at a summation point, and

means for applying the d-c control signal to the slave vco, to maintainsynchronized operation between the master and slave a-c motors.

7. A variable speed motor control system as claimed in claim 6, in whichthe subsystem further comprises a position control unit with avoltage-adjusting portion coupled to the summing means, such thatmovement of the voltage-adjusting portion modifies the d-c controlsignal at the summation point so that a modified d-c signal is appliedto the slave vco, thus producing an incremental position displacement ofthe slave motor relative to the master motor without changing thesynchronized operation of the two motors.

8. A variable speed motor control system as claimed in claim 6, in whichthe summing means includes first and second summing amplifiersindividually coupled to the dacs, and a pair of mixing resistors ofgiven value, each resistor coupled between the summation point and oneof the summing amplifiers, such that the d-c control signal is providedat the summation point by combining the output signals from the summingamplifiers over the mixing resistors.

9. A variable speed motor control system as claimed in claim 8, in whichthe subsystem further comprises an out-of-sync circuit, a third resistorcoupled between the out-of-sync circuit and the summation point, whichthird resistor has a value approximately an order of magnitude less thansaid given value, so that application of an override signal from theout-of-sync circuit swamps the d-c control signal at the summationpoint, thus driving the slave vco in the proper direction to achievesynchronized operation.

10. A variable speed motor control system as claimed in claim 9, inwhich the out-of-sync circuit is connected to receive a first inputsignal from the phase detector connoting in-phase and out-of-phaseoperation, and is also connected to receive a second input signal fromthe phase detector connoting underspeed and overspeed conditions.

1]. variable speed motor control system as claimed in claim 6, in whichthe means for applying the d-c control signal to the slave vco includesan amplifierand-filter circuit having at least one amplifier stage, andhaving a variable resistor connected to adjust the system gain.

12. A variable speed motor control system as claimed in claim 11, inwhich the variable resistor is Y coupled in series with the main signalpath through amplifier-and-filter circuit to adjust the system gain.

13. A variable speed motor control system for driving a first a-c motorenergized from a first inverter which receives timing pulses from amaster source, including a system speed control unit connected toregulate the rate at which the timing pulses issue from the mastersource, a second a-c motor energized from a second inverter whichreceives timing pulses from a slave source, and the improvement whichcomprises a phaselock and position control subsystem including:

means for applying a signal from the system speed control unit to theslave source of timing pulses,

-a phase detector, connected to receive a first series ofposition-indicating signals which varies as a function of movement ofthe first a-c motor and to provide a first reset signal upon receipt ofeach position-indicating signal in the first series, also connected toreceive a second series of positionindicating signals which varies as afunction of movement of the second a-c motor and to provide a secondreset signal upon receipt of each positionindicating signal in thesecond series, and to provide a square wave output signal in which thepositive-going and negative-going portions are determined by the firstand second series of position-indicating signals;

a first function generator, connected to receive an input signal fromthe master source and to provide a first a-c signal with differentparameters, in which one parameter is determined by receipt of saidfirst reset signal from the phase detector,

a second function generator, connected to receive an input signal fromthe slave source and to provide a second a'c signal with differentparameters, one parameter having a polarity opposite that of thecorresponding parameter in the first a-c signal and displaced in phaserelative to the first a-c signal, in which another parameter of thesecond ramp signal is deter-mined by receipt of said second reset signalfrom the phase detector,

summing means for combining the a-c signals with the square wave outputsignal of the phase detector to provide a d-c control signal at asummation point, which d-c control signal has virtually zero ripplevoltage at the low-frequency rate of the position-indicating signals,and

means for applying the d-c control signal to the slave source of timingpulses, to maintain synchronized operation between the first and seconda-c motors.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3,"(118, 814.6 Dated February 27, 1973 Inventofl'S) Benton Bejach It iscertified that error appears in the above-identified patent and, thatsaid Letters Patent are hereby corrected as shown below:v

Column 2, line 22, "syn-chronized" should read 5- synchronized Columnll, line 60, ""in-dicating" should res. indicating Column 5, line 23,"sig-n 'al" should read signal i line 32, "about'nshould read above 7Column 8, line 14.1, out of-sync" should reed out-of-sync Column 13,"line 11 "move-merit" should read movement Column 1);, line 9,"adjusting" should read adjusting v-- line 53 up to and including line22 in column 15 should be cancelled;

Column 16, line 2T, "move -ment" should read I movement line 51,"deter-mined" should reed determined Signed and sealed this 26th day ofFebruary 19714.. I M

(CSEAL) Attest: v

EDWARD M.FLETCHER,JR. "'ETMIREEKIFDRNNH I Attesting Officer Commissionerof Patents FORM Podoso (10.69) I. I I uscoMM-Dc scan-Pea Patent No.

Inventor(s) Benton Bejach Dated February 27, 1973 Column 2, line 22,

line line Column 5,

Column 8, line out-of-sync Column 13, line lL movement Column 11 line-9,

Column 16, line 27', movement determined (SEAL) Attest:

EDWARD M.FLETCHER,J'B. Attesting Officer FORM F'O-105O (10-69) It iscertified that error appears in the above-identified patent and thatsaid Letters Patent are hereby corrected as shown below:v

"in-dicating" should read adjusting v--; line 53 up to and includingline .22 column 15 should be cancelled;

line 51, "deter-mined" should read Signed and sealed this 26th day ofFebruary 19714..

"syn-chronized" should read "sig-nal" should read signal "about" shouldread above "out of-sync" should read "move-ment" should read"ad-justing" should read "move-ment" should read USCOMM'DC 50376-P69U.S. GOVERNMENT PRINTING OFFICE I969 0-355-534.

1. A variable speed motor control system for driving a first a-c motor energized from a first inverter which receives timing pulses from a master source, including a system speed control unit connected to regulate the rate at which the timing pulses issue from the master source, a second a-c motor energized from a second inverter which receives timing pulses from a slave source, and the improvement which comprises a phaselock and position control subsystem, including: means for applying a signal from the system speed control unit to the slave source of timing pulses, a phase detector, connected to receive a first series of position-indicating signals which varies as a function of movement of the first a-c motor and to provide a first reset signal upon receipt of each position-indicating signal in the first series, and also connected to receive a second series of position-indicating signals which varies as a function of movement of the second a-c motor and to provide a second reset signal upon receipt of each position-indicating signal in the second series, a first register-and-dac, connected to receive an input signal from the master source and to provide a first ramp signal with a slope of given polarity, and also coupled to said phase detector so that the reset portion of the first ramp signal is determined by said first reseT signal, a second register-and-dac, connected to receive an input signal from the slave source and to provide a second ramp signal with a slope having a polarity opposite that of the first ramp signal and displaced in phase relative to the first ramp signal, and also coupled to said phase detector so that the reset portion of the second ramp signal is determined by said second reset signal, summing means for combining the ramp signals to provide a d-c control signal at a summation point, and means for applying the d-c control signal to the slave source of timing pulses, to maintain synchronized operation between the first and second a-c motors.
 2. A variable speed motor control system as claimed in claim 1, in which the subsystem further comprises a position control unit, coupled to the summing means, such that adjustment of the position control unit modifies the d-c control signal and produces an incremental position displacement of the second a-c motor with respect to the first a-c motor, without disturbing the synchronized operation between the two motors.
 3. A variable speed motor control system as claimed in claim 1, in which the summing means comprises first and second summing amplifiers respectively coupled to the dacs, and a pair of mixing resistors, each coupled between the summation point and one of the summing amplifiers, such that the d-c control signal is provided at the summation point for application to the slave source of timing pulses.
 4. A variable speed motor control system as claimed in claim 1, in which the subsystem further comprises an out-of-sync circuit connected to receive both a first signal from the phase detector indicating in-phase and out-of-phase operation, and a second signal from the phase detector indicating under-speed and over-speed conditions when the system is out-of-phase, and means coupled between the out-of-sync circuit and the summing means, to override the d-c control signal when the system is out of phase and pass to the slave source a modified d-c signal to drive the system toward in-phase operation.
 5. A variable speed motor control system as claimed in claim 1, in which the subsystem further comprises an amplifier-and-filter circuit, coupled between the summing means and the slave source of timing pulses, including means for adjusting the gain of the system and thus ad-justing variations in the duty cycle of the phase detector to maintain system accuracy.
 6. A variable speed motor control system for driving a master a-c motor energized from a master inverter which receives timing pulses from a master vco, including a system speed control unit connected to regulate the rate at which the timing pulses issue from the master vco, and a slave a-c motor energized from a slave inverter which receives timing pulses from a slave vco, characterized by a phaselock and position control subsystem which includes: means for applying a signal from the system speed control unit to the slave vco, a phase detector, connected to receive a first series of low frequency position indicating signals which varies as a function of movement of the master a-c motor and to provide a first reset signal upon receipt of each position indicating signal in the first series, also connected to receive a second series of low frequency position indicating signals which varies as a function of movement of the slave a-c motor and to provide a second reset signal upon receipt of each position indicating signal in the second series, and also connected to provide a square wave output signal in which the positive-going and negative-going portions are determined by the first and second series of low frequency position indicating signals, a count-up register-and-dac, connected to receive a high frequency input signal from the master vco and to provide a first ramp signal with a positive slope, and also coupled to the phase detector so that the reset portion of the first ramp signal is determined by receipt of said first reset signal, a count-down register-and-dac, connected to receive a high frequency input signal from the slave vco and to provide a second ramp signal with a negative slope, which second ramp signal is displaced in phase with respect to the first ramp signal, and also coupled to the phase detector so that the reset portion of the second ramp signal is determined by receipt of said second reset signal, summing means for combining the positive-slope and negative which the timing pulses issue from the master vco, and a slave a-c motor energized from a slave inverter which receives timing pulses from a slave vco, characterized by a phaselock and position control subsystem which includes: means for applying a signal from the system speed control unit to the slave vco, a phase detector, connected to receive a first series of low frequency position indicating signals which varies as a function of movement of the master a-c motor and to provide a first reset signal upon receipt of each position indicating signal in the first series, also connected to receive a second series of low frequency position indicating signals which varies as a function of movement of the slave a-c motor and to provide a second reset signal upon receipt of each position indicating signal in the second series, and also connected to provide a square wave output signal in which the positive-going and negative-going portions are determined by the first and second series of low frequency position indicating signals, a count-up register-and-dac, connected to receive a high frequency input signal from the master vco and to provide a first ramp signal with a positive slope, and also coupled to the phase detector so that the reset portion of the first ramp sig-nal is determined by receipt of said first reset signal, a count-down register-and-dac, connected to receive a high frequency input signal from the slave vco and to provide a second ramp signal with a negative slope, which second ramp signal is displaced in phase with respect to the first ramp signal, and also coupled to the phase detector so that the reset portion of the second ramp signal is determined by receipt of said second reset signal, summing means for combining the positive-slope and negative-slope ramp signals with the phase detector square wave output signal to provide a d-c control signal at a summation point, and means for applying the d-c control signal to the slave vco, to maintain synchronized operation between the master and slave a-c motors.
 7. A variable speed motor control system as claimed in claim 6, in which the subsystem further comprises a position control unit with a voltage-adjusting portion coupled to the summing means, such that movement of the voltage-adjusting portion modifies the d-c control signal at the summation point so that a modified d-c signal is applied to the slave vco, thus producing an incremental position displacement of the slave motor relative to the master motor without changing the synchronized operation of the two motors.
 8. A variable speed motor control system as claimed in claim 6, in which the summing means includes first and second summing amplifiers individually coupled to the dacs, and a pair of mixing resistors of given value, each resistor coupled between the summation point and one of the summing amplifiers, such that the d-c control signal is provided at the summation point by combining the output signals from the summing amplifiers over the mixing resistors.
 9. A variable speed motor control system as claimed in claim 8, in which the subsystem further comprises an out-of-sync circuit, a third resistor coupled between the out-of-sync circuit and the summation point, which third resistor has a value approximately an order of magnitude less than said given value, so that application of an override signal from the out-of-sync circuit swamps the d-c control signal at the summation point, thus driving the slave vco in the proper direction to achieve synchronized operation.
 10. A variable speed motor control system as claimed in claim 9, in which the out-of-sync circuit is connected to receive a first input signal from the phase detector connoting in-phase and out-of-phase operation, and is also connected to receive a second input signal from the phase detector connoting underspeed and overspeed conditions.
 11. A variable speed motor control system as claimed in claim 6, in which the means for applying the d-c control signal to the slave vco includes an amplifier-and-filter circuit having at least one amplifier stage, and having a variable resistor connected to adjust the system gain.
 12. A variable speed motor control system as claimed in claim 11, in which the variable resistor is coupled in series with the main signal path through amplifier-and-filter circuit to adjust the system gain.
 13. A variable speed motor control system for driving a first a-c motor energized from a first inverter which receives timing pulses from a master source, including a system speed control unit connected to regulate the rate at which the timing pulses issue from the master source, a second a-c motor energized from a second inverter which receives timing pulses from a slave source, and the improvement which comprises a phaselock and position control subsystem including: means for applying a signal from the system speed control unit to the slave source of timing pulses, a phase detector, connected to receive a first series of position-indicating signals which varies as a function of move-ment of the first a-c motor and to provide a first reset signal upon receipt of each position-indicating signal in the first series, also connected to receive a second series of position-indicating signals which varies as a function of movement of the second a-c motor and to provide a second reset signal upon receipt of each position-indicating signal in the second series, and to provide a square wave output signal in which the positive-going and negative-going portions are determined by the first and second series of position-indicating signals; a first function generator, connected to receive an input signal from the master source and to provide a first a-c signal with different parameters, in which one parameter is determined by receipt of said first reset signal from the phase detector, a second function generator, connected to receive an input signal from the slave source and to provide a second a-c signal with different parameters, one parameter having a polarity opposite that of the corresponding parameter in the first a-c signal and displaced in phase relative to the first a-c signal, in which another parameter of the second ramp signal is deter-mined by receipt of said second reset signal from the phase detector, summing means for combining the a-c signals with the square wave output signal of the phase detector to provide a d-c control signal at a summation point, which d-c control signal has virtually zero ripple voltage at the low-frequency rate of the position-indicating signals, and means for applying the d-c control signal to the slave source of timing pulses, to maintain synchronized operation between the first and second a-c motors. 